1. Field of the Invention
This invention relates generally to digital computer systems and specifically to digital computer systems which rely on master-slave latches or flip-flops. The invention provides an apparatus and method for generating quickly slewing clock signals with non-overlapping duty cycles from a master clock that has relatively slow rise and fall times.
2. Description of the Prior Art
Referring to FIG. 1, the current state of the art describes a master-slave latch combination in which data is clocked into the master latch 20 and slave latch 40 through a two sets of gating transistor pairs 10 and 30, respectively, by a master clock CLK and its complement CLK.sup.1. D indicates the input data and Q represents the static state output of D after proper latching by the master latch 20 and the slave latch 40. The master clock signal CLK and its complement CLK are depicted in FIG. 2.
 FNT .sup.1 The conventional method to indicate a complementary signal is to overline the signal. However, due to a word processing limitation, following this convention is not possible. Thus, in the text of this application the symbol for a complementary signal is set for as the signal underlined (e.g. CLK).
When properly operating, the master clock CLK goes from low to high, the gating transistor pair 10 is conducting and data is permitted to pass into the master latch 20. Also at this time, because the clock signals are inverted at gating transistor pair 30, this transistor pair is switched off and data is not permitted to pass into the slave latch 40.
When the master clock CLK reverses state, i.e. from high to low, the first gating transistor pair 10 ceases to conduct. However, the second gating transistor pair 30 begins conducting and the data which was latched into the master latch 20 is now permitted to pass into the slave latch 40. After a brief propagation delay, the data is latched and stable at output Q.
Thus, when the master-slave latch is operating properly, latching occurs in two separate, discrete steps. These two steps provides for stable data at output Q. However, a problem arises during slow rise and fall times of the master clock CLK.
The problem during the clock transition characterized by relatively slow rise and fall times is that both gating transistor pairs 10 and 30 may be partially conducting at the same time. This will result in the data racing through the master-slave latch pair 20 and 40 without achieving a steady state. This occurs when the two step process described above is circumvented because of overlapping master clock signals as a result of relatively slow rise and fall times. Therefore, a need existed to provide a master-slave latch pair with non-overlapping clock signals to permit proper latching of data in a two step process for master-slave latches.